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integrated circuit systems, inc. ics932s801 0959c?03/13/06 functionality pin configuration recommended application: serverworks gc-ht systems using amd k8 processors output features: 4 - pairs of amd k8 clocks 1 - pair of src/pci express* clock 2 - 14.318 mhz ref clocks 2 - usb_48mhz clocks 4 - hypertransport 66 mhz clocks 4 - pci 33 mhz clocks features: spread spectrum for emi reduction outputs may be disabled via smbus m/n programming via smbus k8 clock chip for serverworks gc-ht 2-way servers power groups *other names and brands may be claimed as the property of others. vdd gnd 3 6 48mhz 9 14 66mhz htt clocks 15 20 33 mhz pci clocks 22 23 iref, analo g core 27 28 src pll, srcclk 33,37,41 32,36,40 k8 cpu clocks, cpu pll 48 44 ref clocks, xtal osc illator pin number description cpu htt pci mhz mhz mhz 0 0 0 hi-z hi-z hi-z 001 x x/3 x/6 0 1 0 180.00 60.00 30.00 0 1 1 220.00 73.12 36.56 1 0 0 100.00 66.66 33.33 1 0 1 133.33 66.66 33.33 1 1 0 166.67 66.66 33.33 1 1 1 200.00 66.66 33.33 fs0 fs2 fs1 x1 148 vddref x2 247 fs0/ref0 vdd48 346 fs1/ref1 48mhz_0 445 fs2 48mhz_1 544 gnd gnd 643 cpuclk8t0 sclk 742 cpuclk8c0 sdata 841 vddcpu vddhtt 940 gndcpu httclk0 10 39 cpuclk8t1 httclk1 11 38 cpuclk8c1 httclk2 12 37 vddcpu httclk3 13 36 gndcpu gndhtt 14 35 cpuclk8t2 vddpci 15 34 cpuclk8c2 pciclk0 16 33 vddcpu pciclk1 17 32 gndcpu pciclk2 18 31 cpuclk8t3 pciclk3 19 30 cpuclk8c3 gndpci 20 29 spread_en pd# 21 28 gndsrc vdda 22 27 vddsrc gnda 23 26 srcclkt0 iref 24 25 srcclkc0 48-ssop, tssop ics932s801
2 ics932s801 0959c?03/13/06 pin descriptions pin # pin name pin type description 1x1 in crystal input, nominally 14.318mhz. 2 x2 out cr y stal output, nominall y 14.318mhz 3 vdd48 pwr power pin for the 48mhz output.3.3v 4 48mhz_0 out 48mhz clock output. 5 48mhz_1 out 48mhz clock output. 6 gnd pwr ground pin. 7 sclk i/o clock pin of smbus circuitry, 5v tolerant. 8 sdata i/o data pin for smbus circuitr y , 5v tolerant. 9 vddhtt pwr supply for htt clocks, nominal 3.3v. 10 httclk0 out 3.3v h y per transport output 11 httclk1 out 3.3v hyper transport output 12 httclk2 out 3.3v h y per transport output 13 httclk3 out 3.3v hyper transport output 14 gndhtt pwr gr ound pin for the htt outputs 15 vddpci pwr power supply for pci clo cks, nominal 3.3v 16 pciclk0 out pci clock output. 17 pciclk1 out pci clock output. 18 pciclk2 out pci clock output. 19 pciclk3 out pci clock output. 20 gndpci pwr ground pin for the pci outputs 21 pd# in asynchronous active low input pin used to power down the device. the internal clocks are disabled and the vco and the cr y stal are stopped. 22 vdda pwr 3.3v power for the pll core. 23 gnda out ground pin for the pll core. 24 iref out this pin establishes the reference current for the differential current-mode output pairs. this pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 25 srcclkc0 out complement clock of differential src clock pair. 26 srcclkt0 out true clock of differential src clock pair. 27 vddsrc pwr suppl y for src clocks, 3.3v nominal 28 gndsrc pwr ground pin for the src outputs 29 spread_en in as y nchronous, active hi g h input to enable spread spectrum functionalit y . 30 cpuclk8c3 out complementary clock of differential 3.3v push-pull k8 pair. 31 cpuclk8t3 out true clock of differential 3.3v push-pull k8 pair. 32 gndcpu pwr gr ound pin for the cpu outputs 33 vddcpu pwr suppl y for cpu clocks, 3.3v nominal 34 cpuclk8c2 out complementary clock of differential 3.3v push-pull k8 pair. 35 cpuclk8t2 out true clock of differential 3.3v push-pull k8 pair. 36 gndcpu pwr gr ound pin for the cpu outputs 37 vddcpu pwr suppl y for cpu clocks, 3.3v nominal 38 cpuclk8c1 out complementary clock of differential 3.3v push-pull k8 pair. 39 cpuclk8t1 out true clock of differential 3.3v push-pull k8 pair. 40 gndcpu pwr gr ound pin for the cpu outputs 41 vddcpu pwr suppl y for cpu clocks, 3.3v nominal 42 cpuclk8c0 out complementary clock of differential 3.3v push-pull k8 pair. 43 cpuclk8t0 out true clock of differential 3.3v push-pull k8 pair. 44 gnd pwr ground pin. 45 fs2 in frequenc y select pin. 46 fs1/ref1 i/o frequency select latch input pin / 14.318 mhz reference clock. 47 fs0/ref0 i/o frequenc y select latch input pin / 14.318 mhz reference clock. 48 vddref pwr ref, xtal power s upply, nominal 3.3v
3 ics932s801 0959c?03/13/06 general description the ics932s801 is a main clock synthesizer chip that, when paired with ics9db108, provides all clocks required by serverworks gc-ht-based servers. an smbus interface allows full control of the device. block diagram i r e f cpu pll pciclk(3:0) control logic xtal osc. cpuclk8(3:0) fixed pll 48mhz(1:0) ref(1:0) httclk(3:0) x1 x2 pci33 div htt66 div src pll cpu div s d a t a sclk fs(2:0) spread src div1 srcclk(0) pd# skew characteristics parameter description test conditions skew window unit tsk_cpu_cpu cpu to cpu skew measured at crossing points of cpuclkt rising edges 250 ps tsk_cpu_pci cpu to pci skew meastured at crossing point for cpuclkt and 1.5v for pci clock 2000 ps tsk_pci33-ht66 pci33 to ht66 skew measured between rising edges at 1.5v 500 ps tsk_cpu_ht66 cpu to ht66 skew meastured at crossing point for cpuclkt and 1.5v for ht66 clock 2000 ps tsk_cpu_cpu cpu to cpu skew measured at crossing points of cpuclkt rising edges 200 ps tsk_cpu_pci cpu to pci skew meastured at crossing point for cpuclkt and 1.5v for pci clock 200 ps tsk_pci33-ht66 pci33 to ht66 skew measured between rising edges at 1.5v 200 ps tsk_cpu_ht66 cpu to ht66 skew meastured at crossing point for cpuclkt and 1.5v for ht66 clock 200 ps t i m e v a r i a n t t i m e i n d e p e n e n t
4 ics932s801 0959c?03/13/06 0 0 100.00 0 1 101.00 1 0 102.00 1 1 104.00 srcfs1 b5b3 srcfs0 b5b2 srcclk (mhz) table1: src frequency selection table table 2: cpu divider ratios bit 00 01 10 11 msb 00 0000 2 0100 4 1000 8 1100 16 01 0001 3 0101 6 1001 12 1101 24 10 0010 5 0110 10 1010 20 1110 40 11 0011 15 0111 30 1011 60 1111 120 lsb address div address div address div address div divider (3:2) divider (1:0) table 3: htt divider ratios bit 00 01 10 11 msb 00 0000 4 0100 8 1000 16 1100 32 01 0001 3 0101 6 1001 12 1101 24 10 0010 5 0110 10 1010 20 1110 40 11 0011 15 0111 30 1011 60 1111 120 lsb address div address div address div address div divider (1:0) divider (3:2) table 4: src divider ratios bit 00 01 10 11 msb 00 0000 2 0100 4 1000 8 1100 16 01 0001 3 0101 6 1001 12 1101 24 10 0010 5 0110 10 1010 20 1110 40 11 0011 7 0111 14 1011 28 1111 56 lsb address div address div address div address div divider (1:0) divider (3:2)
5 ics932s801 0959c?03/13/06 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.8v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +3.8 v ambient operating temperature . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . ?65c to +150c esd protection . . . . . . . . . . . . . . . . . . . . . . . . input esd protection usung human body model > 1kv stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage v ih 3.3 v +/-5% 2 v dd + 0.3 v1 input low voltage v il 3.3 v +/-5% v ss - 0.3 0.8 v 1 input high current i ih v in = v dd -5 5 ua 1 i il1 v in = 0 v; inputs with no pull-up resistors -5 ua 1 i il2 v in = 0 v; inputs with pull-up resistors -200 ua 1 operating current i dd3.3op all outputs driven 325 ma powerdown current i dd3.3pd 100 ma in p ut fre q uenc y 3 f i v dd = 3.3 v 14.31818 mhz 3 pin inductance 1 l pin 7nh1 c in logic inputs 5 pf 1 c out output pin capacitance 6 pf 1 c inx x1 & x2 pins 5 pf 1 clk stabilization 1,2 t stab from v dd power-up or de-assertion of pd# to 1st clock 3ms1,2 modulation fre q uenc y trian g ular modulation 30 33 khz 1 smbus voltage v dd 2.7 5.5 v 1 low-level output voltage v ol @ i pullup 0.4 v 1 current sinking at v ol = 0.4 v i pullup 4ma1 sclk/sdata clock/data rise time 3 t ri2c (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata clock/data fall time 3 t fi2c (min vih + 0.15) to (max vil - 0.15) 300 ns 1 1 guaranteed b y desi g n and characterization, not 100% tested in p roduction. 2 see timin g dia g rams for timin g re q uirements. 3 input frequency should be measured at the refout pin and tuned to ideal 14.31818mhz to meet ppm frequency accuracy on pll outputs. input low current input capacitance 1
6 ics932s801 0959c?03/13/06 electrical characteristics - k8 push pull differential pair t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =amd64 processor test load parameter symbol conditions min typ max units notes rising edge rate v / t 210v/ns1 falling edge rate v / t 210v/ns1 differential voltage v diff 0.4 1.25 2.3 v 1 change in v diff_dc ma g nitude ? v diff -150 150 mv 1 common mode voltage v cm 1.05 1.25 1.45 v 1 chan g e in common mode volta g e ? v cm -200 200 mv 1 jitter, cycle to cycle t jcyc-cyc measurement from differential wavefrom. maximum difference of cycle time between 2 adjacent cycles. 0 100 200 ps 1 jitter, accumulated t ja measured usin g the jit2 software package with a tek 7404 scope. tie (time interval error) measurement technique: sample resolution = 50 ps, sam p le duration = 10 s -1000 1000 1,2,3 duty cycle d t3 measurement from differential wavefrom 45 53 % 1 output impedance r on avera g e value durin g switchin g transition. used for determining series termination value. 15 35 55 ? 1 group skew t src-skew measurement from differential wavefrom 250 ps 1 1 guaranteed b y desi g n and characterization, not 100% tested in p roduction. 2 all accumulated j itter s p ecifications are g uaranteed assumin g that ref is at 14.31818mhz 3 s p read s p ectrum is off measured at the amd64 processor's test load. 0 v +/- 400 mv (differential measurement) measured at the amd64 processor's test load. (single-ended measurement)
7 ics932s801 0959c?03/13/06 electrical characteristics - src 0.7v current mode differential pair t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =2pf, r s =33.2 ? , r p =49.9 ?, ref = 475? parameter symbol conditions min typ max units notes current source output im p edance zo v o = v x 3000 ? 1 voltage high vhigh 660 850 1,3 voltage low vlow -150 150 1,3 max volta g e vovs 1150 1 min volta g e vuds -300 1 crossing voltage (abs) vcross(abs) 250 350 550 mv 1 crossing voltage (var) d-vcross variation of crossing over all ed g es 12 140 mv 1 lon g accurac y pp msee t p eriod min-max values -300 300 pp m1,2 100.00 mhz nominal 9.9970 10.0000 10.0030 ns 2 100.00 mhz s p read 9.9970 10.0530 ns 2 absolute min p eriod tabsmin @100.00mhz nominal/s p read 9.8720 ns 1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 700 ps 1 rise time variation d-t r 30 125 ps 1 fall time variation d-t f 30 125 ps 1 duty cycle d t3 measurement from differential wavefrom 45 55 % 1 group skew t src-skew measurement from differential wavefrom n/a ps pci express gen 1 phase jitter cpu=200mhz, s p read off 38 86 ps 1, 4 pci express gen 1 phase jitter cpu=200mhz, s p read on 52 86 ps 1, 4 jitter, cycle to cycle t jcyc-cyc measurement from differential wavefrom 100 ps 1 1 guaranteed b y desi g n and characterization, not 100% tested in p roduction. 2 all lon g term accurac y and clock period s p ecifications are g uaranteed assumin g that ref is at 14.31818mhz 3 i ref = v dd /(3xr r ). for r r = 475 ? (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 ? . 4 per pci sig method for pci ex p ress gen 1. visit htt p ://www. p cisi g .com for details. mv measurement on single ended signal using absolute value. mv statistical measurement on single ended signal using oscilloscope math function. jitter, phase t jphase-pcie1 tperiod average period
8 ics932s801 0959c?03/13/06 electrical characteristics - pciclk 33 mhz, httclk 66 mhz clocks t a = 0 - 70c; vdd=3.3v +/-5%; c l = 20 pf (unless otherwise specified) parameter symbol conditions min typ max units notes lon g accurac y pp m see t p eriod min-max values -300 300 pp m1,2 33.33mhz out p ut nominal 29.9910 30.0090 ns 2 33.33mhz out p ut s p read 29.9910 30.1598 ns 2 66.67mhz out p ut nominal 14.9955 15.0045 ns 2 66.67mhz out p ut s p read 14.9955 15.0799 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.55 v 1 v oh @min = 1.0 v -33 ma 1 v oh @ max = 3.135 v -33 ma 1 v ol @ min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 edge rate v / t rising edge rate 1 4 v/ns 1 ed g e rate v / t fallin g ed g e rate 1 4 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 skew t sk1 v t = 1.5 v 200 ps 1 jitter, cycle to cycle t jcyc-cyc v t = 1.5 v 250 ps 1 1 guaranteed b y desi g n and characterization, not 100% tested in p roduction. 2 all long term accuracy and clock period specifications are guaranteed with the assumption that ref is at 14.31818mhz output high current i oh output low current i ol pci33 clock period t period htt66 clock period t period electrical characteristics - 48mhz t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 20 pf (unless otherwise specified) parameter symbol conditions min typ max units notes lon g accurac y pp m see t p eriod min-max values -100 100 pp m1,2 clock p eriod t p eriod 48.00mhz out p ut nominal 20.8257 20.8340 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.55 v 1 v oh @ min = 1.0 v -33 ma 1 v oh @ max = 3.135 v -33 ma 1 v ol @min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 ed g e rate v / t risin g ed g e rate 1 4 v/ns 1 edge rate v / t falling edge rate 1 4 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 skew t sk1 v t = 1.5 v 50 ps 1 jitter, cycle to cycle t jcyc-cyc v t = 1.5 v 200 ps 1 1 guaranteed b y desi g n and characterization , not 100% tested in p roduction. output low current i ol 2 all long term accuracy and clock period specifications are guaranteed with the assumption that ref is at 14.31818mhz output high current i oh
9 ics932s801 0959c?03/13/06 electrical characteristics - ref-14.318mhz t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 27 pf (unless otherwise specified) parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values -300 300 ppm 1 clock period t p eriod 14.318mhz output nominal 69.8270 69.8550 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 output high current i oh v oh @min = 1.0 v, v oh @max = 3.135 v -29 -23 ma 1 output low current i ol v ol @min = 1.95 v, v ol @max = 0.4 v 29 27 ma 1 ed g e rate v / t risin g ed g e rate 1 2 v/ns 1 edge rate v / t falling edge rate 1 2 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 skew t sk1 v t = 1.5 v 50 ps 1 jitter, cycle to cycle t jcyc-cyc v t = 1.5 v 1000 ps 1 1 guaranteed b y desi g n and characterization, not 100% tested in p roduction. 2 all long term accuracy and clock period specifications are guaranteed with the assumption that ref is at 14.31818mhz
10 ics932s801 0959c?03/13/06 general smbus serial interface information how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 (see note 2) ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
11 ics932s801 0959c?03/13/06 smbus table: frequency select and spread control register pin # name control function t yp e0 1pwd bit 7 fs source latched input or smbus frequency select rw latched inputs smbus 0 bit 6 cpu ss_en rw off on 0 bit 5 src ss_en rw off on 0 bit 4 reserved reserved rw reserved reserved 0 bit 3 fs3 freq select bit 3 rw 0 bit 2 fs2 freq select bit 2 rw latched bit 1 fs1 freq select bit 1 rw latched bit 0 fs0 freq select bit 0 rw latched smbus table: output control register pin # name control function t yp e0 1pwd bit 7 pciclk3 output enable rw disable (low) enable 1 bit 6 pciclk2 output enable rw disable (low) enable 1 bit 5 pciclk1 output enable rw disable (low) enable 1 bit 4 pciclk0 output enable rw disable (low) enable 1 bit 3 httclk3 output enable rw disable (low) enable 1 bit 2 httclk2 output enable rw disable (low) enable 1 bit 1 httclk1 output enable rw disable (low) enable 1 bit 0 httclk0 output enable rw disable (low) enable 1 smbus table: output control register pin # name control function t yp e0 1pwd bit 7 48mhz_1 output enable rw disable (low) enable 1 bit 6 48mhz_0 output enable rw disable (low) enable 1 bit 5 ref1 output enable rw disable (low) enable 1 bit 4 ref0 output enable rw disable (low) enable 1 bit 3 cpuclk8(3) r w disable enable 1 bit 2 cpuclk8(2) r w disable enable 1 bit 1 cpuclk8(1) r w disable enable 1 bit 0 cpuclk8(0) rw disable enable 1 output enable when disabled cpuclkt = 0 cpuclkc = 1 - - - - - b y te 1 spread enable for cpu and src plls. setting spread_en to '1', forces spread on for both plls. b y te 0 - - - b y te 2 see functionality table on page 1
12 ics932s801 0959c?03/13/06 smbus table: srcclk(0) output control register pin # name control function type 0 1 pwd bit 7 reserved reserved rw reserved reserved 0 bit 6 reserved reserved rw reserved reserved 0 bit 5 reserved reserved rw reserved reserved 0 bit 4 reserved reserved rw reserved reserved 0 bit 3 reserved reserved rw reserved reserved 0 bit 2 reserved reserved rw reserved reserved 0 bit 1 srcclk0 pd srcclk power down drive mode rw driven hi-z 0 bit 0 srcclk0 output enable rw disable (hi-z) enable 1 smbus table: 48mhz drive strength control register pin # name control function type 0 1 pwd bit 7 reserved reserved rw reserved reserved 0 bit 6 reserved reserved rw reserved reserved 0 bit 5 reserved reserved rw reserved reserved 0 bit 4 reserved reserved rw reserved reserved 0 bit 3 reserved reserved rw reserved reserved 0 bit 2 reserved reserved rw reserved reserved 0 bit 1 48mhz_1 ds drive stren g th control rw 1x 2x 0 bit 0 48mhz_0 ds drive strength control rw 1x 2x 0 smbus table: src frequency select register pin # name control function type 0 1 pwd bit 7 reserved reserved rw reserved reserved 0 bit 6 reserved reserved rw reserved reserved 0 bit 5 reserved reserved rw reserved reserved 0 bit 4 reserved reserved rw reserved reserved 0 bit 3 srcfs1 src fs bit 1 rw 0 bit 2 srcfs0 src fs bit 0 rw 0 bit 1 reserved reserved rw reserved reserved 0 bit 0 reserved reserved rw reserved reserved 0 smbus table: device id register pin # name control function type 0 1 pwd bit 7 devid 7 device id msb r - - 1 bit 6 devid 6 device id 6 r - - 0 bit 5 devid 5 device id 5 r - - 0 bit 4 devid 4 device id4 r - - 0 bit 3 devid 3 device id3 r - - 0 bit 2 devid 2 device id2 r - - 0 bit 1 devid 1 device id1 r - - 0 bit 0 devid 0 device id lsb r - - 1 - - - - - see table 1: src frequency select byte 5 - - - - 5 4 byte 6 - - - - - - - - byte 4 - - - - byte 3 - - - - - - - -
13 ics932s801 0959c?03/13/06 smbus table: vendor id register pin # name control function type 0 1 pwd bit 7 rid3 r - - x bit 6 rid2 r - - x bit 5 rid1 r - - x bit 4 rid0 r - - x bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 smbus table: byte count register pin # name control function type 0 1 pwd bit 7 bc7 rw 0 bit 6 bc6 rw 0 bit 5 bc5 rw 0 bit 4 bc4 rw 0 bit 3 bc3 rw 1 bit 2 bc2 rw 0 bit 1 bc1 rw 0 bit 0 bc0 rw 1 smbus table: reserved register pin # name control function t yp e0 1pwd bit 7 reserved reserved rw reserved reserved 0 bit 6 reserved reserved rw reserved reserved 0 bit 5 reserved reserved rw reserved reserved 0 bit 4 reserved reserved rw reserved reserved 0 bit 3 reserved reserved rw reserved reserved 0 bit 2 reserved reserved rw reserved reserved 0 bit 1 reserved reserved rw reserved reserved 0 bit 0 reserved reserved rw reserved reserved 0 smbus table: m/n programming enable pin # name control function type 0 1 pwd bit 7 m/n_en cpu and src pll m/n pro g rammin g enable rw disable enable 0 bit 6 reserved reserved rw - - 0 bit 5 reserved reserved rw - - 0 bit 4 reserved reserved rw - - 0 bit 3 reserved reserved rw - - 0 bit 2 reserved reserved rw - - 0 bit 1 reserved reserved rw - - 0 bit 0 reserved reserved rw - - 0 byte 8 byte 7 - - - writing to this register will configure how many bytes will be read back, default is 9 bytes. - - - - - - - - - - - byte 10 byte 9 - - - - - - - revision id vendor id (0001 = ics) - byte count programming b(7:0) - - - - - - - - - -
14 ics932s801 0959c?03/13/06 smbus table: cpu frequency control register pin # name control function t yp e0 1pwd bit 7 n div8 n divider prog bit 8 rw x bit 6 n div9 n divider prog bit 9 rw x bit 5 m div5 rw x bit 4 m div4 rw x bit 3 m div3 rw x bit 2 m div2 rw x bit 1 m div1 rw x bit 0 m div0 rw x smbus table: cpu frequency control register pin # name control function t yp e0 1pwd bit 7 n div7 rw x bit 6 n div6 rw x bit 5 n div5 rw x bit 4 n div4 rw x bit 3 n div3 rw x bit 2 n div2 rw x bit 1 n div1 rw x bit 0 n div0 rw x smbus table: cpu spread spectrum control register pin # name control function t yp e0 1pwd bit 7 ssp7 rw x bit 6 ssp6 rw x bit 5 ssp5 rw x bit 4 ssp4 rw x bit 3 ssp3 rw x bit 2 ssp2 rw x bit 1 ssp1 rw x bit 0 ssp0 rw x smbus table: cpu spread spectrum control register pin # name control function t yp e0 1pwd bit 7 reserved reserved r - - 0 bit 6 ssp14 rw x bit 5 ssp13 rw x bit 4 ssp12 rw x bit 3 ssp11 rw x bit 2 ssp10 rw x bit 1 ssp9 rw x bit 0 ssp8 rw x spread spectrum programming bit(7:0) - - - - - - b y te 11 - - m divider programming bit (5:0) - - - - - n divider programming byte12 bit(7:0) and byte11 bit(7:6) - - spread spectrum programming bit(14:8) - - - - - - - - - - b y te 14 - - - b y te 13 b y te 12 - - - - these spread spectrum bits in byte 13 and 14 will program the spread pecentage of cpu these spread spectrum bits in byte 13 and 14 will program the spread pecentage of cpu the decimal representation of m and n divier in byte 11 and 12 will configure the cpu vco frequency. default at power up = latch - in or byte 0 rom table. vco frequency = 14.318 x [ndiv(9:0)+8] / [mdiv(5:0)+2] the decimal representation of m and n divier in byte 11 and 12 will configure the cpu vco frequency. default at power up = latch - in or byte 0 rom table. vco frequency = 14.318 x [ndiv(9:0)+8] / [mdiv(5:0)+2]
15 ics932s801 0959c?03/13/06 smbus table: src frequency control register pin # name control function t yp e0 1pwd bit 7 n div8 n divider prog bit 8 rw x bit 6 n div9 n divider prog bit 9 rw x bit 5 m div5 rw x bit 4 m div4 rw x bit 3 m div3 rw x bit 2 m div2 r w x bit 1 m div1 r w x bit 0 m div0 rw x smbus table: src frequency control register pin # name control function t yp e0 1pwd bit 7 n div7 rw x bit 6 n div6 rw x bit 5 n div5 rw x bit 4 n div4 rw x bit 3 n div3 rw x bit 2 n div2 r w x bit 1 n div1 r w x bit 0 n div0 rw x smbus table: src spread spectrum control register pin # name control function t yp e0 1pwd bit 7 ssp7 rw x bit 6 ssp6 rw x bit 5 ssp5 rw x bit 4 ssp4 r w x bit 3 ssp3 r w x bit 2 ssp2 r w x bit 1 ssp1 r w x bit 0 ssp0 rw x smbus table: src spread spectrum control register pin # name control function t yp e0 1pwd bit 7 reserved reserved r - - 0 bit 6 ssp14 rw x bit 5 ssp13 rw x bit 4 ssp12 rw x bit 3 ssp11 rw x bit 2 ssp10 rw x bit 1 ssp9 r w x bit 0 ssp8 rw x - - m divider programming bits - - b y te 16 spread spectrum programming b(7:0) - - - spread spectrum programming b(14:8) - - - - - - these spread spectrum bits in byte 17 and 18 will program the spread pecentage of src n divider programming b(7:0) - these spread spectrum bits in byte 17 and 18 will program the spread pecentage of src - - - - - - - - - b y te 18 b y te 17 - - - - - - - - b y te 15 - the decimal representation of m and n divier in byte 15 and 16 will configure the src vco frequency. default at power up = latch - in or byte 0 rom table. vco frequency = 14.318 x [ndiv(9:0)+8] / [mdiv(5:0)+2] the decimal representation of m and n divier in byte 15 and 16 will configure the src vco frequency. default at power up = latch - in or byte 0 rom table. vco frequency = 14.318 x [ndiv(9:0)+8] / [mdiv(5:0)+2]
16 ics932s801 0959c?03/13/06 smbus table: programmable output divider register pin # name control function type 0 1 pwd bit 7 cpudiv3 rw x bit 6 cpudiv2 rw x bit 5 cpudiv1 rw x bit 4 cpudiv0 rw x bit 3 httdiv3 rw x bit 2 httdiv2 rw x bit 1 httdiv1 rw x bit 0 httdiv0 rw x smbus table: programmable output divider register pin # name control function type 0 1 pwd bit 7 reserved reserved r - - x bit 6 reserved reserved r - - x bit 5 reserved reserved r - - x bit 4 reserved reserved r - - x bit 3 src_div3 rw x bit 2 src_div2 rw x bit 1 src_div1 rw x bit 0 src_div0 rw x smbustable: test byte register test t yp epwd bit 7 rw 0 bit 6 rw 0 bit 5 rw 0 bit 4 rw 0 bit 3 rw 0 bit 2 rw 0 bit 1 rw 0 bit 0 rw 0 ics only test reserved byte 21 ics only test reserved ics only test reserved ics only test reserved ics only test reserved ics only test reserved ics only test reserved test function test result ` ics only test reserved - - byte 19 - - - - - - - - byte 20 - - - - - - see table 2: cpu divider ratios see table 3: htt divider ratios see table 4: src divider ratios cpu divider ratio programming bits htt divider ratio programming bits (pci divider is always 2x the htt divider or 1/2 freq.) src_ divider ratio programming bits
17 ics932s801 0959c?03/13/06 fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) on the ics932s801 serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k figure 1 shows a means of implementing this function when a switch or 2 pin header is used. with no jumper is installed the pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, than only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
18 ics932s801 0959c?03/13/06 ordering information ics932s801 y flft example: index area index area 12 1 2 n d h x 45 h x 45 e1 e seating plane seating plane a1 a e -c- - c - b .10 (.004) c .10 (.004) c c l designation for tape and reel packaging rohs compliant package type f = ssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device ics xxxx y f - lf t min max min max a2.412.80.095.110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c0.130.25.005.010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h0.380.64.015.025 l0.501.02.020.040 n a 0808 variations min max min max 48 15.75 16.00 .620 .630 10-0034 0.635 basic 0.025 basic common dimensions in millimeters in inches common dimensions reference doc.: jedec publication 95, mo-118 300 mil ssop n see variations see variations d mm. d (inch) symbol see variations see variations
19 ics932s801 0959c?03/13/06 ordering information ics932s801 y glft example: designation for tape and reel packaging rohs compliant package type g = tssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device ics xxxx y g - lf t in d ex a r ea in d ex a r ea 1 2 1 2 n d e1 e s eatin g p lane s eatin g p lane a1 a a 2 a 2 e - c - - c - b c l aaa c min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n a0808 aaa -- 0.10 -- .004 variations min max min max 48 12.40 12.60 .488 .496 10-0039 n d mm. d (inch) reference doc.: jedec publication 95, mo-153 0.50 basic 0.020 basic see variations see variations see variations see variations 8.10 basic 0.319 basic (240 mil) (20 mil) symbol in millimeters in inches common dimensions common dimensions
20 ics932s801 0959c?03/13/06 revision history rev. issue date description page # b 5/18/2005 1. updated electrical characteristics tables: i) changed src jitter from 125ps to 100ps; ii) changed pci/htt skew from 500ps to 200ps; iii) added usb skew, 50ps. iv) change ref skew from 500ps to 50ps. 2. updated lf orderin g information from "lead free" to "rohs compliant". 14-16 18-19 c 3/13/2006 1. correct pin description of pd# (pin 21). it does not contain a pull up resistor. 2. added pcie gen 1 phase noise numbers to src output characterisitics 2, 7

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